Sequential circuits occupy around 50% of a digital design. Integrated clock gating (ICG) technique is used to reduce power consumption by preventing individual flip flops from switching between logic states when not in use. Thus, the clock power consumption due to clock switching is reduced. In integrated clock gating, the flip flops which are not contributing to the functionality of the circuit are selectively deactivated. The ICG cells are activated or deactivated based on certain conditions. The conditions for disabling the clock cells are a design choice. In advanced digital designs, several clock gating cells are used which results in increased power consumption.
In power critical digital designs, more flip-flops are required to be clock gated which proportionately increases the number of ICG cells in the digital design. In an example, when sequential circuit occupy 50% of the digital design, and an ICG cell drives clock input to 4 flops, the ICG cell occupy around 5 to 7% of the digital design. A comparison of percentage of power consumption between the units of the IC are logic implementation consuming 29%, flip flops consuming 27%, RAM consuming 18%, clock tree consuming 16% and the ICG consuming 10% of the total power. It is apparent that a reduction in the power consumption and/or area of ICG cell will directly improve the overall power consumption of the digital design.